1. Field of the Invention
The embodiments of the invention generally relate to complementary metal oxide semiconductor (CMOS) devices and, more particularly, to a method of forming a CMOS device having an electroplated high-aspect ratio metal replacement gate.
2. Description of the Related Art
Prior art complementary metal oxide semiconductor (CMOS) technologies are typically manufactured with a gate stack that includes a thin silicon oxide (SiO2) gate dielectric layer and a doped-polysilicon gate conductor layer. With device size scaling, the desired gate dielectric thickness has been reduced. Unfortunately, doped polysilicon gate conductors are subject to depletion effects and, thereby increase the effective gate dielectric thickness. Thus, conventional gate structures are not suitable for future CMOS technology generations and, more particularly, for CMOS technology generations beyond the 65 nm node. Rather in order to realize the power requirements of CMOS transistors at the 65 nm node and beyond, gates stacks that include a metal gate conductor layer, which is not subject depletion effects, as well as a high-k dielectric layer, which minimizes gate leakage current, will be required. Therefore, there is a need in the art for a CMOS device structure and a method of forming the structure that incorporates a high-k gate dielectric-metal gate conductor gate stack.